In most computer systems including central processing units (CPU) and main memories, the speed for decoding and executing instructions or operands is dependent on how fast the instructions or operands are transferred to the CPU from the main memory.
To shorten the transmission time, a cache memory 106 is interposed between a CPU 102 and a main memory 104 as shown in FIG. 1. The cache memory 106 is relatively small in size and acts as a buffer memory to temporally store data of the memory 104, which reduces access time for fetching data or operands from/to the CPU or the main memory. The cache memory is generally composed of a plurality of blocks (or lines) each of which is associated with an address tag to designate there is a duplicate of data of the memory when the CPU requests the data (or refers the main memory for the data). After comparison of the address tags, a requested block absent in the cache memory is detected from the main memory and, being stored in the cache memory, then provided to the CPU.
U.S. Pat. No. 5,091,851 describes a cache memory system of a multi-way set associative cache type. The multi-way set associative cache memory allows the date processing speed to be accelerated by providing simultaneous accesses to plural data random-access memories (RAMs) with an index. In the cache memory, a set is defined as an assemblage of all lines accessible by one cache index and the number of data RAMs accessible by one cache index represents the number of ways. For instance, one with two data RAMs accessed by one index is referred to as two-way set associative cache memory. If a comparison result with the address tag notes that a requested data block belongs to a specific data RAM, a reading or writing operation is carried out for the specific data RAM.
Referring to FIG. 2, a traditional cache memory 106 includes tag RAMs, 202 and 204, data RAMs 206 and 208, tag comparators 210 and 212, gates 214 and 216, a multiplexer 218, and an OR gate 220.
When requesting data from the cache 106, the CPU 102 offers an address for reading on a line 222. A typical address format is shown in FIG. 3. An address 300 with 32 bits is composed of the field of an address tag 302 of bits 0˜20, a cache index 304 of bits 21˜25, a line offset 306 of bits 26˜29, and a byte offset 308 of bits 30˜31.
Data stored in the data RAMs 206 and 208 are associated with 16 lines of word, each RAM retaining 32 lines. Each data line in the data RAM is addressable by the cache index 304. The tag RAM 202 stores an address tag for each data line of the data RAM 206, and the tag RAM 204 stores an address tag for each data line of the data RAM 208. The same cache index simultaneously designates address tags in the tag RAMs 204 and 206 to select relevant data lines therein.
The cache index in the read address 300 is used in accessing an address tag on a current data line in the data RAM 206 at a specific position of the tag RAM 202. The tag RAM 202 loads an address tag on a line 224. Tag comparator 210 compares an address tag of the rag RAM 202 with an address tag of the read address 300. If the two address tags are identical, the tag comparator 210 generates a valid signal to a line 226 to transfer it to the OR gate 220 and the gate 214. However, as a control signal on an input line 228 disables the gate 214, the valid signal on the line 226 cannot be transferred to a write-enable input line 230 for the data RAM 206.
At the same time with the access to an address tag of the tag RAM 202, the cache index 304 and the line offset 306 of the read address 300 are used to access to a data word in the data RAM 206. The data word of the data RAM 206 is loaded on an output line 230. The valid signal on the line 226 makes the multiplexer 218 connect the data of the output line 230 to a line 232. And then, the data on the line 232 is transferred to the CPU 102. If the address tag of the tag RAM 202 is not in accord with the address tag of the read address 300, an invalid signal is loaded on the line 226 from the tag comparator 210, informing the tag RAM 202 of a miss state.
While being utilized in the tag RAM 202 and the data RAM 206, the cache index in the read address 300 is used in accessing an address tag on a current data line in the data RAM 208 at a specific position of the tag RAM 204. The tag RAM 204 loads an address tag on a line 234. Tag comparator 212 compares an address tag of the rag RAM 204 with an address tag of the read address 300. If the two address tags are identical, the tag comparator 212 generates a valid signal to a line 236 to transfer it to the OR gate 220 and the gate 216. However, as a control signal on an input line 238 disables the gate 216, the valid signal on the line 236 cannot be transferred to a write-enable input line 240 for the data RAM 208.
At the same time with the access to an address tag of the tag RAM 204, the cache index 304 and the line offset 306 of the read address 300 are used to access a data word in the data RAM 208. The data word of the data RAM 2085 is loaded on an output line 242. The valid signal on the line 236 makes the multiplexer 218 connect the data of the output line 242 to a line 232. Then, the data on the line 232 is transferred to the CPU 102. If the address tag of the tag RAM 204 is not in accord with the address tag of the read address 300, an invalid signal is loaded on the line 236 from the tag comparator 212, informing the tag RAM 204 of a miss state.
When the tag comparators 210 and 212 generate the invalid signals, a signal informing of a cache miss state appears at an output line 244 of the OR gate 220. Then, a data line of the main memory 104, containing a word designated by the address, is selectively connected to the data RAM 206 or the data RAM 208 from the main memory. An address tag for the selected data line is applied to the tag RAM 202 or the tag RAM 204.
In the operating features of the conventional multi-way set associative cache, the signal obtained from the result in the tag comparator 210 or 212, referred to as a “set selection signal”, controls the multiplexer 218. All the data from the multiple sets are read from the data RAMs and selected by the multiplexer 218.
Referring to FIG. 4, which illustrates a typical functional feature like the conventional multi-way set associative cache system with such a multiplexer, as shown in FIG. 2, a tag comparator 608 generates a set selection signal that is applied to a multiplexer 610 (corresponding to 218 in FIG. 2) to select one of data from L2 cache RAMs 606 (i.e., the data RAMs 206 and 208) after comparing an address tag of tag RAMs 604 (i.e., the tag RAMS 202 and 204) with an address tag of a read address provided from an MPU 602 (i.e., the CPU 102). The selected data from the multiplexer 610 is transferred to an output buffer 612.
However, power consumption increases when a read operation is performed in multiple sets to obtain data in a given cycle time. Moreover, power consumption may further increase due to a high number of data lines from the data RAMs to the multiplexer and a number of data bits to be accessed therein.
Also, considering that a read path, through which the set selection signal from the tag comparator is applied to the data RAM to read data stored in the cache, is involved in capacitive loads with lines and circuit blocks, the overall operation speed in the cache system is very dependent on how fast the set selection signal arrives at the cache from the tag RAM. But, although a conventional set selection buffer uses a clock signal to operate the data access with synchronized timing, there is a limit of data transmission because it takes a time until the clock signal is active even while the set selection signal has been enabled.